The manufacturing of prior art displays often adopts the design of gate driver on array (GOA), in which the gate switch circuit of a Thin Film Transistor (TFT) is integrated on the array substrate of a display panel. In this way, a bonding area for the gate driver circuit and a peripheral wiring space can be omitted, thus realizing the aesthetic design of a narrow frame for the display panel.
FIG. 1 illustrates a schematic diagram of a conventional GOA circuit, in which only two cascaded GOA circuit cells are shown, and the corresponding terminals in these two GOA cells, except for the current-stage output terminal (OUT_x, x=1, 2, 3, . . . ), are denoted with the same reference signs. In FIG. 1, CK and CKB are clock signals with opposite phase, CN and CNB are complementary direct current (DC) levels for controlling the forward and reverse scanning directions, STV_N−1 and STV_N+1 are respectively input signals for the forward and reverse scanning, STV_N is a generated intermediate scanning signal, and OUT_1 and OUT_2 are gate driving pulses provided for different pixel rows. When CN is a high level and CNB is a low level, the forward scanning is performed, wherein gate driving pulses are sequentially output on OUT_1, OUT_2, . . . OUT_n (n is the number of pixel rows) as excited by STV_N−1 applied to the first-stage GOA cell. On the contrary, when CN is a low level and CNB is a high level, the reverse scanning is performed, wherein gate driving pulses are sequentially output on OUT_n, OUT_n−1, . . . OUT_1 as excited by STV_N+1 applied to the last-stage GOA cell. In this conventional GOA circuit, each row of pixels needs a corresponding GOA circuit cell to generate a gate driving pulse. Thereby, it requires a huge number of GOA circuit cells, such that the GOA circuit occupies a relatively large frame space, which is disadvantageous for further narrowing the display screen frame.
Therefore, an improved GOA circuit arrangement is needed.